Dear Readers,


One of our friends had some difficulty on "Testcase Parameters & Contents/Template of the test-case file"

Victor of Edaplayground.com has answered this query and due credit goes to Victor 

Lets understand how the  test case parameters can be driven inside the test bench environment  & the contents/template of the test case file?



In UVM, we typically use the uvm_config_db to parametrize the verification environment with methods like:
uvm_config_db#(string)::set
uvm_config_db#(string)::get

And +uvm_set_config_* options from the command line

References 


1)https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/base/uvm_cmdline_processor-svh.html#uvm_cmdline_processor.+uvm_set_config_int,+uvm_set_config_string

2)These  methods are used  in this UVM 1.2 example: 
http://www.edaplayground.com/s/4/1032


-Happy Reading
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