Dear Readers

First let me Wish you all Happy festive days
Please feel free to email me with your suggestions/feedback and i am open for any constructive ideas which makes this small effort get better

We all know that UVM has the following simulation phase methods-Build time,run time & clean up 

UVM Simulation phase methods can be classified as build,connect, end of elaboration, start of simulation, run and clean up phases(extract, check,report)

Build ,connect, end of elaboration ,start of simulation, run, extract, check,report ,Final

Out of these phases ONLY build is the top down method and all others are bottom up methods ,all phase methods except RUN are functions and RUN is a  task.

So lets see what actually happens in each and every simulation phase method here 

During the build phase the factory is called and used to Construct various child components/ ports/exports and configured,the top level testbench topology is built 

During the connect phase the TLM connections are made and the ports/exports of the components are Connected. i.e, the environment topology is connected.

During the end of elaboration the connections are checked and used for configuring the components. Post elaboration activity and the topology is printed 

During the start of simulation the various files are opened  banner information /topology would be being printed (as below)

# ----------------------------------------------------------------

# UVM-1.0p1 

# (C) 2007-2011 Mentor Graphics Corporation

# (C) 2007-2011 Cadence Design Systems, Inc.

# (C) 2006-2011 Synopsys, Inc.

# ----------------------------------------------------------------

During the run phase main test is executed and simulation is run
UVM adds 12 new phases which would be executed in parallel  with run_phase
These 12 new phases would be used to control stimulus which is explained as below

pre_reset,
reset
post_reset
pre_config
config
post_config
pre_main
main
post_main
pre_shutdown
shutdown
post_shutdown

The stimulus control being done by the objection mechanism, lets see the codes

class my_test_phase extends uvm_test_phase;
//Factory registration
//Use component utils macro as its TB component
`uvm_component_utils(my_phase_test)
//Boiler Plate code which is mandatory for all UVM TB components
function new(string name ,uvm_component_parent)
super.new(name,parent);
//Boiler plate code end
endfunction

task ..._phase(uvm_phase phase)
phase.raise_objection(this, "Starting Phase");
//Sequence start
//end Sequence
phase.drop_objection(this, "Finished Phase");
endtask

endclass


Drivers and monitors would be using JUST this run_phase

During the extract, check, report,Final phase methods post processing is done and the required information /details are gathered on the final state of the DUT,results are checked for the extracted information and the test pass/fail reporting would be done.

One of the differences  between OVM and UVM is that there is no final phase method in ovm.

-Happy Reading
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