Some more information which may be useful

1)What is the difference between the Push/Pull interfaces in TLM communication

    with the Push interface control and data go in the same direction

    with the pull interface control and data go in the opposite direction

2)In the Sequence items do we randomize the input/output properties

In the Sequence item, we randomize the input properties which contain address/data

3) What does a clone do?

       A clone returns uvm_object

4)Advantage of Virtual interface

Through the Virtual interface classes connect to Physical pins in System Verilog

5)Analysis port & the difference between the regular ports

Analysis port is a regular port which supports broadcast mechanism
It can be connected to a single export /no export/multiple exports also called subscribers
Regular ports are 1:1 where as analysis port are 1:many or none

6)Sequences and the transactions are customizable via the factory pattern
  Sequences, Transactions,Sequence _items are dynamic and created at run time where as Sequencer/driver are static like components