Dear Readers
Posting some more Q&A i was asked during the interviews.Please feel free to add anything to make this better
-Happy Reading
Hash
Q) Why do we use/advantages of Virtual Sequencers in UVM?
Ans :
To run Virtual Sequence
Virtual sequences are required when more than one interfaces are required to drive sequence items.
When there is dependencies on various interfaces its always better to write a virtual sequence.
In verif Env, there are always one or more interfaces. Every sequence-sequncer-driver flow is attached/refer to one interface. Generally we can sequences form testcase, if there are more than one interface, we can use fork-join to trigger them parallel, but in case we need to generate some sequence/scenario of individual sequences it will be helpful to use virtual sequencer, which will have instances of various interface sequencers , which then can be controlled form virtual sequencer as per the requirement. For example, if some interface used to configure the register & rest of traffic happens through another interface, such controlling of sequences can be easily done through virtual sequencer. Alternatively we can also use virtual sequences.
Q) Why is the run phase in UVM again divided into Sub phases?
What is the advantage of the sub phases (run) in UVM?
Ans:
Run phases are sub divided in 4 phases.
Mainly used in asynchronous reset condition.
Abnormal run_phase termination.
Run phase is only task & consumes time. It actually starts the individual sequences & generates traffic. Within run phase it may require to play around with reset/clk ,which generally happens in tb_top initial begin-end (clk generation/reset generation), or in run phase we may need to reprogram some registers. To do so either we need to write/use sequences to do so rst/clk/register programming, but having run phase divided in to various barriers or phases, which can go back and re do things will save efforts or writing sequences. So before starting your normal traffic sequences one can use reset an other sub phases. But somehow those are not RECOMMENDED .
Q) what are the layers in the UVM ?
Ans:
Generally in networking domain, there are protocol layers i.e. one protocol above the other. In verif testbench , the main interface agent's sequence has another layer above it, meaning instead of actual interface sequence, there is another form of it, then we can build layering of sequencers, translators sequence , which converts upper level protocol to actual bub interface sequence and has instance of upper layer sequencer, and sends the translated sequence to lower bus protocol, so in short, layers of sequencers are used to achieve layering of protocol implementation
May be Interface Layer, Signal Layer (Driver), Application Layer (Test/Generator).
Q)Do do you enable objections from the command line from any simulation tool?
Ans:
NO, I don't think so , as it should be done explicitly in the code
Q) Why do we need objections in UVM?
Ans:
In UVM, end of test or end of simulation is controller by raising & dropping objections. For example in run phase or sub phases had build in mechanism called as phase_done. The objection mechanism tried to end phase instantly. A sequence must raise the objection when it starts & drop it when it finishes. That way end of simulation is closely controlled by user
Posting some more Q&A i was asked during the interviews.Please feel free to add anything to make this better
-Happy Reading
Hash
Q) Why do we use/advantages of Virtual Sequencers in UVM?
Ans :
To run Virtual Sequence
Virtual sequences are required when more than one interfaces are required to drive sequence items.
When there is dependencies on various interfaces its always better to write a virtual sequence.
In verif Env, there are always one or more interfaces. Every sequence-sequncer-driver flow is attached/refer to one interface. Generally we can sequences form testcase, if there are more than one interface, we can use fork-join to trigger them parallel, but in case we need to generate some sequence/scenario of individual sequences it will be helpful to use virtual sequencer, which will have instances of various interface sequencers , which then can be controlled form virtual sequencer as per the requirement. For example, if some interface used to configure the register & rest of traffic happens through another interface, such controlling of sequences can be easily done through virtual sequencer. Alternatively we can also use virtual sequences.
Q) Why is the run phase in UVM again divided into Sub phases?
What is the advantage of the sub phases (run) in UVM?
Ans:
Run phases are sub divided in 4 phases.
Mainly used in asynchronous reset condition.
Abnormal run_phase termination.
Run phase is only task & consumes time. It actually starts the individual sequences & generates traffic. Within run phase it may require to play around with reset/clk ,which generally happens in tb_top initial begin-end (clk generation/reset generation), or in run phase we may need to reprogram some registers. To do so either we need to write/use sequences to do so rst/clk/register programming, but having run phase divided in to various barriers or phases, which can go back and re do things will save efforts or writing sequences. So before starting your normal traffic sequences one can use reset an other sub phases. But somehow those are not RECOMMENDED .
Q) what are the layers in the UVM ?
Ans:
Generally in networking domain, there are protocol layers i.e. one protocol above the other. In verif testbench , the main interface agent's sequence has another layer above it, meaning instead of actual interface sequence, there is another form of it, then we can build layering of sequencers, translators sequence , which converts upper level protocol to actual bub interface sequence and has instance of upper layer sequencer, and sends the translated sequence to lower bus protocol, so in short, layers of sequencers are used to achieve layering of protocol implementation
May be Interface Layer, Signal Layer (Driver), Application Layer (Test/Generator).
Q)Do do you enable objections from the command line from any simulation tool?
Ans:
NO, I don't think so , as it should be done explicitly in the code
Q) Why do we need objections in UVM?
Ans:
In UVM, end of test or end of simulation is controller by raising & dropping objections. For example in run phase or sub phases had build in mechanism called as phase_done. The objection mechanism tried to end phase instantly. A sequence must raise the objection when it starts & drop it when it finishes. That way end of simulation is closely controlled by user
