MY BRUSH WITH ASIC

Friday 2 September 2016

Dear Readers

Found something interesting , posting for wider audience.
Due credit if any goes to the Author of the article

https://vlsiwithvikas.blogspot.in/2016/06/handshake-mechanism-driver-or-sequence.html
https://vlsiwithvikas.blogspot.in/2016/06/the-overlooked-gems-of-uvm-uvm-report.html

Some more interesting articles

https://dvcon-india.org/sites/dvcon-india.org/files/archive/2015/proceedings/72_UVM_Callbacks_vs_Factory.pdf

Happy Reading
-Hash

Monday 3 August 2015

Dear Readers

I found this paper good to understand UVM, hope you would also like it

https://s3.amazonaws.com/verificationacademy-news/DVCon2015/Papers/dvcon-2015_UVM-Sans-UVM-Automating-UVM-Testbench-Writing-Paper.pdf

Happy Reading
Hash

Saturday 25 July 2015

Dear Readers

I was on OVM for some time and could not find much time to update this blogpost.
However I found this blogpost good, hope you also find it useful

http://learnuvmverification.com/2015/05/14/uvm-environment-components/

-Happy reading
Hash

Friday 4 July 2014

Dear Readers

I found these web resources interesting for UVM,

http://blog.verificationgentleman.com/
https://eda-playground.readthedocs.org/en/latest/_static/uvm-1.2/files/overviews/intro-txt.html

&
http://whatisverification.blogspot.in/2014/06/sequences-in-uvm12.html

Hope you also find them useful

-Happy Reading
Hash

Dear Readers

Lets discuss few things about the task body of a sequence .We know that a sequence is made up of N sequence items and has a task body() which differentiates a sequence from the sequencer code

Lets understand the what does the task body does

1. It contains how many transactions would be sent to the driver
2 . It has to create , randomize, start and finish the transactions.

Hope this is useful.Would post more code going forward.

-Happy Reading
Hash

Tuesday 27 May 2014

Dear Readers

Found this article on "UVM Sequence Library " interesting!
Posting here for wider audience ,hope you find it useful

http://whatisverification.blogspot.in/2014/04/sequence-library-in-uvm.html?utm_source=feedburner&utm_medium=email&utm_campaign=Feed:+whatisverification+(sid%27dha-karana)

-Happy Reading
Hash

Wednesday 21 May 2014

Dear Readers,

Lets talk about the concept of verbosity in UVM, UVM_LOW,UVM_HIGH,UVM_MEDIUM

Lets try to understand this with an example - Think of UVM_LOW/MEDIUM/HIGH as stones of various sizes and take a basic sand filter. If we set the filter size as low , the stone which are bigger than the size of the filter would not be through .
I.e if the filter is set to MEDIUM the stones which are LOW/MEDIUM would be through the filter and HIGH would not be there .If we set the filter is set to HIGH then we can see the LOW/MEDIUM/HIGH would be through.

If we apply the same concept to UVM and set the verbosity as UVM_MEDIUM in the log file we can see the messages UVM_LOW,UVM_MEDIUM and UVM_HIGH would be filtered out
The same way if we set the verbosity to UVM_HIGH everything LOW/HIGH/MEDIUM would be present in the log file JUST think the filter as simulation filter

-Happy Reading
Hash

Sunday 11 May 2014

Dear Readers

While doing mock interviews this afternoon, came across this "what would be the difference between an object & component in UVM" ,thought of posting here

1) Objects are means of communication between components
2)Objects can created and destroyed may times in over all simulation
3)Where as component are created only and once created they remain the same thou the simulation
4)Objects don't have phases and components have phases
5)Example of a component- all uvm components such as sequence item, sequencer.
6) Objects can be overridden and so can be the components by the factory
7) components have hierarchy and objects will not have hierarchy i.e the parent is agent is env, parent to env is test case

-Happy Reading

Hash

Friday 9 May 2014

Dear Readers

Found out these technical tutorials on UVM very interesting,take a look @ http://videos.accellera.org/uvmnownext/uvm349db45sh/index.html

Hope you find it good

-Happy Learning
Hash

Dear Readers

JUST posting a discussion on "differences between UVM Transaction & an UVM object from Verification academy. As it is well answered in the forum lets directly refer to the thread and let i find it good https://verificationacademy.com/forums/uvm/difference-between-uvm-transaction-and-uvm-object

Hope you find it useful

-Happy Reading
Hash

Wednesday 7 May 2014

Dear Readers

One of our friends has a question about special ports( below) in UVM and how these ports are used in communication and what type of applications we may require this kind of ports.

uvm_blocking_put_imp_decl
uvm_blocking_master_imp_decl
`uvm_master_imp_decl etc...

As we know in UVM communication between the various components is by connecting ports to the suitable exports .

These special ports (above) are different variations of TLM API and can find more about these special ports on https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/tlm1/uvm_tlm_ifs-svh.html

Due credit goes to Victor Lyuboslavsky for answering this

-Happy Reading
Hash

Dear Readers

One of our friends has a question on Custom Phases of UVM. Would try to post as much information (i have) on this and would keep updating this post.

As we all know that UVM phases build,connect, end of elaboration, start of simulation,run, extract, check and report.

The concept of custom phases is an advertised feature of UVM, if we want to insert a phase called my_phase we can do so by the concept of custom phases.

Lets see how and where this custom phase(s) i,e my_phase can be inserted in the UVM phases with an example(coming soon).Would explore more on this and update this post

Between take a look at an example of the UVM 1.2 phase introspection API @http://www.edaplayground.com/s/4/1085

-Happy Reading
Hash

Disclaimer: This is a small forum where i keep updating learnt from various online resources/People/attended training's and any due credit goes to them-the experts

Friday 25 April 2014

Dear Readers

Lets discuss some more things about the factory pattern -Where we use/don't use factory pattern in the UVM test bench

1)To run the test by registering with the factory
If you want to run any test i.e my_test it should be registered with the factory pattern

2)for all the UVM test bench components

UVM test bench components like driver/monitor/scoreboard/sequencer

3)For all the objects in the UVM test bench
4)Not for the static connections

As Factory is used for dynamic interconnections we can not use factory pattern for interfaces, coverage,cover groups,TLM ports/FIFOs

-Happy Reading
Hash

Tuesday 15 April 2014

Dear Readers

Lets consider an UVM TB (With a connected DUT) with the data(i.e the sequence items) flowing in and out of the DUT. This data would be stored in the class based format which would be from uvm_sequence_item or uvm_sequence

-Happy Reading
Hash

Monday 24 March 2014

Dear Readers

Found this http://colorlesscube.com/uvm-guide-for-beginners/ really good to get started on UVM along with Cluelogic.

Hope you would find it useful

-Happy Reading
Hash

Tuesday 18 March 2014

Dear Readers,

One of our friends had some difficulty on "Testcase Parameters & Contents/Template of the test-case file"

Victor of Edaplayground.com has answered this query and due credit goes to Victor

Lets understand how the test case parameters can be driven inside the test bench environment & the contents/template of the test case file?

In UVM, we typically use the uvm_config_db to parametrize the verification environment with methods like:
uvm_config_db#(string)::set
uvm_config_db#(string)::get

And +uvm_set_config_* options from the command line

References

1)https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/base/uvm_cmdline_processor-svh.html#uvm_cmdline_processor.+uvm_set_config_int,+uvm_set_config_string

2)These methods are used in this UVM 1.2 example:
http://www.edaplayground.com/s/4/1032

-Happy Reading
Hash

Wednesday 26 February 2014

Dear Readers

Lets write small piece of code to print UVM Library version number using Verilog.

2)You can also refer to

http://www.dvteclipse.com/uvm-1.1-HTML_API/summary-macro-global.html
http://www.edaplayground.com/x/4_y

-Happy Reading
Hash

**********************************************************************
module dummy_printer();
initial
begin
$display("*****************");
$display(`UVM_VERSION_STRING);
$display("******************");
end
endmodule

-- Compiling module dummy_printer

Top level modules:
dummy_printer
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 -sv_lib uvm_dpi dummy_printer
# Loading sv_std.std
# Loading work.dummy_printer
# onElabError resume
# resume
# run -all
# *****************
# UVM-1.1d
# ******************
*********************************************************************************************

Thursday 13 February 2014

Dear Readers

Was going through UVM forums and came across this "running a test" /tests per simulation",thought would add some more information and post it here.

Command line

My_Simulator +UVM_TESTNAME=my_test1

Test:-

Lets understand about the test (my_test1 ) aka test scenario is a time consuming sequence in UVM ,could be a virtual sequence.An UVM test builds TB architecture , decides what sequence(s) are to be run ,end of test ,test pass/fail mechanism .There can be ONLY one test per simulation

Lets understand "Test scenario can be possibly a virtual sequence".Let's assume the user has test1 that runs sequence1 and test2 that runs sequence2.

We can create a higher level sequence (virtual sequence), and this sequence should start sequence1 and then start sequence2. Then can have a single test that runs that virtual sequence.

This is a case of sequence calling a sequence (nested sequences)?
b) If Yes, the test1 can be a single high level sequence(Virtual sequence) which can keep calling N sequences from within ? This way , with a single test we can execute/cover all/most scenarios ?

Yes. There are several ways to do it.A sequence must run on a sequencer but it can be started by another sequence. A sequencer (virtual or not) is a structural uvm component which is created during build phase. A sequence (sequence_item) can be created any time.

So, in the original example, the virtual sequencer would have the handles to the original sequencer1 and sequencer2 for sequence1 and sequence2.. The virtual sequence can get those handles like: p_sequencer.sequencer1

-Happy Reading
Hash

Wednesday 12 February 2014

Dear Readers

I loved these articles on "Re-Usable sequences & Virtual sequences " on VIP Central
Hope you also find these interesting

http://www.vip-central.org/2012/11/reusable-sequences-in-uvm/
http://www.vip-central.org/2012/11/virtual-sequences-in-uvm-why-how/

-Happy Reading
Hash

Wednesday 22 January 2014

Dear Readers

Take a look at video series introducing the features/changes in the upcoming UVM 1.2.

Victor Lyuboslavsky of edaplayground.com put a post on Accellera forums
I personally liked it as there is no dead code and no snapshots of code.

http://forums.accellera.org/topic/1671-uvm-12-introduction-and-code-examples/#entry6346

To know what has changed in UVM1.2 take a look at this youtube video

http://www.youtube.com/embed/V2l4lBlsh7k?list=SPScWdLzHpkAdYPk_jgxRgOPisTm3-7U6A&vq=hd720

-Happy Reading
Hash

Friday 10 January 2014

Dear Readers

Lets talk again about the basic difference between Sequencers & Virtual Sequencers

The basic difference between them is Virtual Sequencers are independent of protocol where as Sequencers are protocol /interface specific for that particular transaction

Thereby Virtual Sequencers control protocol /interface Sequencers and executes Virtual Sequences to control Protocol/Interface Sequences!

Hope you find it useful

-Happy Reading
Hash

Thursday 2 January 2014

Dear Readers

Best Wishes for a Happy & Wonderful New year.

Would schedule some effort to post more code,UVC's ,Advanced UVM in 2014.

Feel free to share your feedback/comments to make it better

-Happy Reading
Hash

Tuesday 17 December 2013

Dear Readers

One of our friends had a small confusion in build Phase of a UVM component.

Question:- In some components the sub components are initialized by “new()” function, sometimes the sub components are initialized using “create()” method inside build method.
So how to understand in what scenario this different ways is followed.

Victor Lyuboslavsky of edaplayground.com has explained it nicely as below ,due credit goes to Victor

Using create() method does two things:

- register the component in the UVM hierarchy. create() must be used for structural components such as uvm_env, uvm_scoreboard, uvm_driver, etc.
- allow the code at a higher level (like at uvm_test) to override the type of component returned. It is a use of the Factory design pattern (https://en.wikipedia.org/wiki/Factory_design_pattern )

So, in short, only use new() if the component is not part of the UVM hierarchy (like a sequence item) AND you will never need to override that component with something else (like another subclass).

Hope you find this useful. All due credit to Victor Lyuboslavsky ,thanks a lot Victor

-Happy Reading
Hash

Disclaimer : This is JUST a small place where i keep updating of small things i know of.
Am NO expert in UVM and i learn from all possible resources available and post it here for my OWN understanding.Due credit goes to the resources/authors

Wednesday 11 December 2013

Dear Readers

Is it possible to covert all Errors into either Warnings/Info in UVM ?
If Yes,lets try to covert all UVM_ERRORS to either Warnings/Info with a small example

Yes , it is possible per UVM1.1 Class reference guide _Final_06062011.pdf ,page no 62

set_report_severity_override
function void set_report_severity_override(uvm_severity cur_severity,uvm_severity new_severity )

set_report_severity_id_override
function void set_report_severity_id_override(uvm_severity cur_severity,string id,uvm_severity new_severity )

These methods provide the ability to upgrade or downgrade a message in terms of severity given severity and id. An upgrade or downgrade for a specific id takes precedence over an upgrade or downgrade associated with a severity

Sample code coming up EOB 12/15.

-Happy Reading
Hash

Dear Readers

ModelSim is JUST added to EDA Playground, which supports SystemVerilog & UVM [everything except SV coverage, SV assertions & randomize() method] and now we can run UVM code on EDA Playground.

Take a look at simple UVM TB @ http://www.edaplayground.com/s/example/546

Hope you find this useful

-Happy Reading
Hash

Friday 29 November 2013

Dear Readers

Planning to write code for a clean compile UVC , stay tuned

2) More on TLM ,UVM Connect

-Happy Reading
Hash

Wednesday 27 November 2013

Dear Readers,

protocol verification -some thoughts

For any protocol verification we can always generate a UVM TB
Lets see what all minimum TB components we should have - a monitor & interface signals for DUT Pins

A scoreboard is good if we want/need to track the history/state of the protocol.
A driver is only needed when the TB is ACTIVE -- if we need to send responses on the bus or to create traffic.

Scenario-1

Lets think of a scenario of no DUT & ONLY "interface" for the pins of the DUT.
Is it possible to simulate UVM components without DUT?

Yes.It is even possible to simulate your UVM components without the DUT.

Please use the SV Unit framework to simulate a UVM driver:

take a look http://www.edaplayground.com/s/example/205

-Happy Reading
Hash

Sunday 24 November 2013

Dear Readers

Came across this interesting web while looking for sometime,find some time to take a look
Those who do not have access to a simulator but want to write test benches in UVM would fnd it real useful.

All you need to do is write the design and T/B in your favorite text editor and copy it here in your free time or you can also write can code the design & TB here

We can ONLY compile but cant simulate on this public version of EDA playground. we can simulate regular Verilog,OVL,MyHDL ,cocotb

http://www.edaplayground.com

-Happy Reading
Hash

Friday 25 October 2013

Dear Readers

I found this Youtube Video - UVM by Mentor real good and easier to learn.
Hope you would find this interesting!

http://www.youtube.com/watch?v=kA7jiowZq3w

-Happy Reading
Hash

Tuesday 22 October 2013

Dear Readers

Let us take a look at coding the following things one step at a time in a series of steps
Initially we would understand the basic template, populate the list of files (in step-1) with an example

-Happy Reading
Hash

Step1) List of files

Sequence item i.e my_simple_sequence_item.sv
Sequencer i.e my_simple_sequencer.sv
Driver i.e my_simple_driver.sv
Env i.e my_simple_env.sv
How to run the test i.e my_simple_program.sv

Step2)Templates

Lets take a look at the default templates for each of the above files

a)my_simple_sequence_item.sv

What does this my_simple_sequence_item contain- This would contain all signals ,constraints, transfers

a)Include uvm macros
b)As UVM is made of classes & libraries ,lets declare class my_simple_sequence_item which would be extended from uvm_sequence_item

********************************************************************************
//Include uvm macros
import uvm_pkg::*;
`include "uvm_macros.svh"
// Code begin line #1
class my_simple_sequence_item extends uvm_sequence_item;

//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints
//Code end
endclass : my_simple_sequence_item
*********************************************************************************

Step-3)Codes

a)my_simple_sequence_item.sv

********************************************************************************
//Include uvm macros
import uvm_pkg::*;
`include "uvm_macros.svh"
// Code begin line #1
class my_simple_sequence_item extends uvm_sequence_item;
rand bit [3:0] a,b;
rand bit [31:0] c[];
constraint valid {c.size inside {[2:50]};}
`uvm_object_utils_begin(my_simple_sequence_item)
`uvm_field_int(a,UVM_ALL_ON)
`uvm_field_int(b,UVM_ALL_ON)
`uvm_field_array_int(c,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "my_simple_sequence_items");
super.new(name);
endfunction
//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints
//Code end
endclass : my_simple_sequence_item
*********************************************************************************

b)my_simple_sequencer.sv

*********************************************************************************

//`include "uvm_macros.svh"
import uvm_pkg::*;
class my_simple_sequencer extends uvm_sequencer #(my_simple_sequence_item);
`uvm_sequencer_utils(my_simple_sequencer)
function new(string name,uvm_component parent);
super.new(name,parent);
`uvm_update_sequence_lib_and_item(my_simple_sequence_item)
endfunction
endclass

*********************************************************************************

c)my_simple_driver.sv

********************************************************************************
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_driver extends uvm_driver #(my_simple_sequence_item);
`uvm_component_utils(my_simple_driver)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual task run();
forever begin
seq_item_port.get_next_item(req);
uvm_report_info("Normal" , "This is a simple_driver item");
req.print();
seq_item_port.item_done();
end
endtask
endclass

********************************************************************************

d)my_simple_env.sv

********************************************************************************
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_env extends uvm_component;
my_simple_sequencer sequencer;
my_simple_driver driver;
`uvm_component_utils_begin(my_simple_env)
`uvm_field_object(sequencer,UVM_DEFAULT)
`uvm_field_object(driver,UVM_DEFAULT);
`uvm_component_utils_end

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual function void build();
super.build();
sequencer = new("sequencer", this);
driver = new("driver",this);
endfunction
virtual function void connect();
super.connect();
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
endclass

*********************************************************************************

e)my_simple_program.sv

********************************************************************************

`include "my_simple_sequence_item.sv"

`include "my_simple_sequencer.sv"

`include "my_simple_driver.sv"

`include "my_simple_env.sv"

program dummy_progrm;

//Import the uvm_package

import uvm_pkg::*;

`include "uvm_macros.svh"

class my_test extends uvm_component;

//Factory registration

`uvm_component_utils(my_test)

my_simple_env env;

//Boiler plate code start

function new (string name,uvm_component parent);

super.new(name,parent);

endfunction

function void build();

env=my_simple_env::type_id::create("env",this);

endfunction

//Boiler plate code end

virtual task run();

uvm_test_done.raise_objection(this);

uvm_report_info("Message","my_test");

uvm_top.print_topology();

uvm_test_done.drop_objection(this);

global_stop_request();

//Print what all types are available in the factory

factory.print();

//Print the TB structure

uvm_top.print_topology();

endtask

//standard phase methods

endclass

initial begin

uvm_default_printer = uvm_default_tree_printer;

fork

run_test("my_test");

#500 global_stop_request();

join

uvm_top.print_topology();

end

endprogram

*********************************************************************************

f)Log

*********************************************************************************
# ----------------------------------------------------------------
# UVM-1.1b
# (C) 2007-2012 Mentor Graphics Corporation
# (C) 2007-2012 Cadence Design Systems, Inc.
# (C) 2006-2012 Synopsys, Inc.
# (C) 2011-2012 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test my_test...
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_random_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_exhaustive_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_simple_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_INFO @ 0: uvm_test_top [Message] my_test
# ......................///////////////////////////////////////////////////////
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
# env: (my_simple_env@511) {
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# }
# }
#
#
#### Factory Configuration (*)
#
# Instance Overrides:
#
# Requested Type Override Path Override Type
# ----------------- -------------------------------- -----------------------
# uvm_sequence_item uvm_test_top.env.sequencer*.item my_simple_sequence_item
#
# No type overrides are registered with this factory
#
# All types registered with the factory: 43 total
# (types without type names will not be printed)
#
# Type Name
# ---------
# my_simple_driver
# my_simple_env
# my_simple_sequence_item
# my_simple_sequencer
# my_test
# questa_uvm_recorder
# (*) Types with no associated type name will be printed as <unknown>
#
####
#
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
# env: (my_simple_env@511) {
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# }
# }
#
# UVM_INFO verilog_src/uvm-1.1b/src/base/uvm_objection.svh(1120) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 7
# UVM_WARNING : 3
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Message] 1
# [Questa UVM] 2
# [RNTST] 1
# [TEST_DONE] 1
# [UVMTOP] 2
# [UVM_DEPRECATED] 3
# ** Note: $finish : C:/modeltech64_10.1c/win64/../verilog_src/uvm-1.1b/src/base/uvm_root.svh(408)

# Time: 0 ns Iteration: 184 Instance: /dummy_progrm
*********************************************************************************

Disclaimer : This is just a small effort to learn UVM and all feedback is welcome

Saturday 19 October 2013

Dear Readers

Let us get started on how to build a UVM testbench given a DUT and timing diagrams in a series of steps.
Take a dummy DUT as below.

Step-1

Lets discuss the various components of a UVM testbench

1)Sequencer Class
2)Driver Class
3)Scoreboard Class
4)Ports
5)Virtual Interface
6)Top Level module
7)Interface
8)Analysis Port
9)Environment

Step-2

Lets map all the components above in step-1 to UVM
UVM testbench with all the mentioned components(Block diagram coming up)

Step-3

Lets look at a dummy DUT Pint out (Coming up soon)

Step-4

Lets have the timing diagrams for the dummy DUT (Coming up soon)

Step-5

Once we have a dummy DUT,timing diagrams and lets see how to build a UVM testbench

Step-6

Lets list down the required files for the UVM testbench as below

1)Sequencer i.e my_sequencer.sv (Class based)
2)Driver i.e my_driver.sv (Class based)
3)Scoreboard i.e my_scoreboard.sv (Class based)
4)Top module i.e my_top.sv
5)Interface i.e my_interface.sv
6)Environment i.e my_env.sv
7)Monitor i.e my_monitor.sv
8)Sequence i.e my_sequence.sv
9)Test i.e my_test.sv
10)Agent i.e my_agent.sv
11)Seq item i.e my_seq_item.sv
12)Config db i.e my_config_db.sv

Step-7

Lets populate the codes for the files in step-6(Coming up soon)

-Happy Reading
Hash

Disclaimer

This is JUST to give a basic understanding in terms of -Look & feel of UVM testbench-Various components-what all files we need to create for a UVM testbench and how to populate the files to get started. Its a small effort to create an UVM testbench given a DUT and timing diagram and the codes MAY NOT BE CLEAN COMPILE at the moment.

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